`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   20:33:15 10/20/2012
// Design Name:   Paddle_Unit
// Module Name:   C:/Users/Maria Victoria/workspace/Pong/TestDePaddle.v
// Project Name:  Pong
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Paddle_Unit
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TestDePaddle;

	// Inputs
	reg clk_i;
	reg reset_sync;
	reg up_sync;
	reg down_sync;

	// Outputs
	wire [9:0] paddle_y;

	// Instantiate the Unit Under Test (UUT)
	Paddle_Unit uut (
		.clk_i(clk_i), 
		.reset_sync(reset_sync), 
		.up_sync(up_sync), 
		.down_sync(down_sync), 
		.paddle_y(paddle_y)
	);

	initial begin
		// Initialize Inputs
		clk_i = 0;
		reset_sync = 0;
		up_sync = 0;
		down_sync = 1;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
   always #20 clk_i <= ~clk_i;    
endmodule

